The present invention relates to a memory circuit and, more particularly, to a memory circuit which has electrical characteristics independent of the change of a source voltage and in which a signal delay due to wiring is reduced.
In attempting to facilitate improvements of memory circuits, various kinds of electrical characteristics have been considered over the years, such as the lowering of an operating voltage of a semiconductor memory to enhance the memory storage capacity and the battery driving to be readily realized.
One procedure of the improvements is to have electrical characteristics independent of the change of a source voltage or an ambient temperature. Another procedure thereof is to reduce a signal delay due to wiring when providing a large memory storage capacity.
The description hereinbelow will be directed to a current source circuit, of a prior art scheme, used in a selection circuit of a sense amplifier circuit used in a static random access memory (SRAM), for discussing the relative change of characteristics thereof to the change of a source voltage. In FIG. 4 shown in JP-A-64922 there is shown an electrical arrangement in which a current source for driving a current amplifier is constructed of an NMOS transistor of which the gate terminal thereof is controlled by a selection signal from a decoder circuit.
The description will hereinbelow be given with respect to the operation of a current source, providing a controllable current, for selecting a memory row which is used in a sense amplifier of a SRAM, such as shown in FIG. 1.
In FIG. 1, numeral 10 designates three MOS transistors each constituting a current source, and numeral 11 designates an input terminal for a signal used for activating the MOS transistors (MOSFETs) 10 and a circuit driven by the MOS transistors 10. Numeral 12 designates a pair of bipolar transistors together constituting a bipolar transistor type differential sense amplifier, the reference numeral 14 designates bipolar transistors configured as emitter followers and reference numeral 13 designates diode-configured bipolar transistors which operate in conjunction with transistors 14 as a level shift circuit for converting a level of a read signal from a memory cell.
Numeral 15 designates a data bus line (e.g., a pair of complementary lines) to which the collectors of the bipolar transistors 12 are connected in common therewith (hereinafter, referred to as "a common collector line", when applicable), and numeral 16 designates a P-channel MOS (PMOS) transistor for adjusting a level of a data bus. Numeral 17 designates a data bus line (hereinafter, referred to as a "common data line", when applicable) used for selecting data from one pair of a plurality of pairs of data lines 19 to transfer the selected one to a sense amplifier, and numeral 18 designates a transfer MOS transistor for selecting one pair of data lines 19 including a memory cell holding the data to be outputted to the common data line 17 (hereinafter, referred to as "a Y switch MOS transistor", when applicable). Numeral 19 designates the data line, numeral 20 designates a word line for inputting therethrough a signal used for selecting one memory cell from a plurality of memory cells connected to one pair of data lines, and numeral 21 designates a memory cell (in the figure, although only one memory cell is shown, practically the memory cells having the number of 128 to 1024 or so are connected to the same pair of data lines). Numeral 22 designates a PMOS transistor for a data line load which is turned off when writing data to the memory cell, and numeral 23 designates a PMOS transistor for a data line load which is normally turned on. Numeral 24 designates a signal terminal which is made to go to "high" in the writing operation thereby to turn the PMOS transistor 22 off, and numeral 25 designates a Y switch signal input terminal used for selecting the Y switch MOS transistor 18. Numeral 26 designates a Y switch terminal used for selecting a Y switch MOS transistor which is shown at the right end in FIG. 1 from the plurality of data lines connected to the common data line 17, and numeral 27 designates the Y switch MOS transistor. Numeral 28 designates wirings of other pairs of Y switch MOS transistors which are not shown in the figure but are connected to the common data lines 17, and numeral 29 designates a bipolar transistor used for shortening a period of time required for the sensing operation and for realizing a high speed operation by reducing the amplitude of the signal on the common collector line.
Numeral 30 designates a constant current source for applying a bias current to the emitter of the bipolar transistor 29, and numeral 31 designates a constant current source for applying a bias voltage to the base of the bipolar transistor 29. Numeral 34 designates a resistor for generating an output amplitude of a sense amplifier stage, and numeral 35 designates a resistor for supplying a base bias of the bipolar transistor 29. Numeral 36 designates an output terminal (e.g., a pair of complementary output terminals) of the sense amplifier stage, and numeral 37 designates a memory block which has a number of memory cells connected to the same sense amplifiers. Moreover, numeral 38 represents a power source terminal and numeral 39 represents the ground terminal.
The operation will subsequently be described. For the operation of reading out data from the memory cell, it is necessary to select the memory row including the memory cell which holds the data to be outputted on the data bus lines (i.e., the common collector lines 15). In the circuit shown in FIG. 1, the operation of selecting the data in the memory row is realized by operating the current source for driving the sense amplifier. That is, in the case shown in FIG. 1, the memory row is selected by turning the MOS transistors 10 constituting the current source on.
The problem inherent in the current source selection method employed in the above-mentioned prior art sense amplifier is that the electrical characteristics largely depend on the power source voltage. Since in the above example, the MOS transistors 10 are driven by a CMOS logic circuit, the selection signal having substantially the same amplitude (the amplitude of the CMOS logical level) as that of the power source voltage is applied to the gate terminal 11. When the power source voltage applied to the semiconductor apparatus is raised or lowered in accordance with the change of the external conditions, the gate voltage of the MOS transistor 10 is changed along therewith to vary the magnitude of the current generated by the current source. Since generally, the change in current level of a MOS transistor is approximately proportional to a change of the gate bias voltage squared, that change becomes large. However, such a large change in current level is not desirable from a point of view of the stability of the circuit performance to the external power source voltage.
As shown in the above example, in an electric circuit, generally, such a current is required in some cases to be substantially zero in the off period and constant in the on period, independently of the external conditions such as the power source voltage of the apparatus, the ambient temperature and the change of the device characteristics due to the variations in the process.
Moreover, signal delay due to the wiring becomes a problem as the storage capacity of the memory is increased.
When the storage capacity of the memory is increased, as shown in FIG. 2, the output signals of sense amplifiers PS1 and PS2 in a first stage are transferred through data bus lines CC1 and CC2 of several mm length. A data bus line becomes increased in length as the level of integration is increased, and the width thereof becomes narrowed as the degree of scale down is advanced. Therefore, the resistance of the wiring of the data bus line is increased. In a similar manner, when the pitch of the data bus line is decreased, the capacitance between the wirings is also increased. As described above, the wiring resistance and the wiring capacitance are increased. Therefore, since the delay of the signal line is increased, the high integration and the high speed performance cannot be attained at the same time. As a method of solving this problem, hitherto, there is known an example in which a data bus line is divided by a data multiplexer which employs a multi-emitter and is disclosed in JP-A-2-244491 to divide a resistance and a capacitance, thereby to attain the high integration and the high speed performance simultaneously.
The prior art data multiplexer employing the multi-emitter has the disadvantage in which when the power source voltage becomes less than 3.3 V, the normal operation cannot be obtained. That reason will now be described when applying the improved construction of the current source circuit to the general multiplexer circuit shown in FIG. 3. In a circuit shown in FIG. 3, the voltage drop across MP1 and MP2, serving as a current source as well as a selection logic circuit, is about 1 V, the voltage drop across each of QP1 and QP2 is about 0.8 V, and voltage drop across each of QME1 and QME2 is about 0.8 V. Further, since load resistors are provided between the collectors of QME1 and QME2 and VCCL, the output voltage amplitude occurs in each of the collectors and the voltage drop of about 0.8 V is developed thereacross. Therefore, the total voltage drop between the potential at the VCCL terminal and the ground potential through QME1, QP2, MP1 and MP2 is 3.4 V. As a result, in the prior art multiplexer circuit, the operation at the source voltage of 3.3 V cannot be performed. Further, in an LSI of high integration, it is required to provide a multiplex in a hierarchical manner. However, in the prior art multiplexer, such an arrangement cannot be realized.